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quad-channel digital isolators adum1410/ADUM1411/adum1412 rev. e information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features low power operation 5 v operation 1.3 ma per channel max @ 0 mbps to 2 mbps 4.0 ma per channel max @ 10 mbps 3 v operation 0.8 ma per channel max @ 0 mbps to 2 mbps 1.8 ma per channel max @ 10 mbps bidirectional communication 3 v/5 v level translation high temperature operation: 105c up to 10 mbps data rate (nrz) programmable default output state high common-mode transient immunity: >25 kv/s 16-lead, pb-free, soic wide body package safety and regulatory approvals ul recognition: 2500 v rms for 1 minute per ul 1577 csa component acceptance notice #5a vde certificate of conformity (pending) din en 60747-5-2 (vde 0884 part 2): 2003-01 din en 60950 (vde 0805): 2001-12; en 60950: 2000 v iorm = 560 v peak applications general-purpose multichannel isolation spi? interface/data converter isolation rs-232/rs-422/rs-485 transceiver industrial field bus isolation functional block diagrams encode decode encode decode encode decode encode decode v dd1 gnd 1 v ia v ib v ic v id disable gnd 1 v dd2 gnd 2 v oa v ob v oc v od ctrl gnd 2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 adum1410 06502-001 figure 1. adum1410 functional block diagram decode encode encode decode encode decode encode decode v dd1 gnd 1 v ia v ib v ic v od ctrl 1 gnd 1 v dd2 gnd 2 v oa v ob v oc v id ctrl 2 gnd 2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ADUM1411 06502-002 figure 2. ADUM1411 functional block diagram decode encode decode encode encode decode encode decode v dd1 gnd 1 v ia v ib v oc v od ctrl 1 gnd 1 v dd2 gnd 2 v oa v ob v ic v id ctrl 2 gnd 2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 adum1412 06502-003 figure 3. adum1412 functional block diagram general description the adum141x 1 are four-channel digital isolators based on analog devices, inc. i coupler? technology. combining high speed cmos and monolithic air core transformer technologies, these isolation components provide outstanding performance characteristics superior to alternatives such as optocoupler devices. by avoiding the use of leds and photodiodes, i coupler devices remove the design difficulties commonly associated with opto- couplers. the usual concerns that arise with optocouplers, such as uncertain current transfer ratios, nonlinear transfer functions, and temperature and lifetime effects are eliminated with the simple i coupler digital interfaces and stable performance charac- teristics. the need for external drivers and other discrete components is eliminated with these i coupler products. furthermore, i coupler devices consume one-tenth to one-sixth the power of optocouplers at comparable signal data rates. the adum141x isolators provide four independent isolation channels in a variety of channel configurations and data rates (see the ordering guide ) up to 10 mbps. all models operate with the supply voltage on either side ranging from 2.7 v to 5.5 v, providing compatibility with lower voltage systems as well as enabling voltage translation functionality across the isolation barrier. all products also have a default output control pin. this allows the user to define the logic state the outputs are to adopt in the absence of the input power. unlike other optocoupler alternatives, the adum141x isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions and during power-up/power-down conditions. 1 protected by u.s. patents 5,952,849, 6, 873,065 and 7,075,329. other patents pending.
adum1410/ADUM1411/adum1412 rev. e | page 2 of 20 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagrams............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 electrical characteristics5 v operation................................ 3 electrical characteristics3 v operation................................ 5 electrical characteristicsmixed 5 v/3 v or 3 v/5 v operation....................................................................................... 7 package characteristics ............................................................. 10 regulatory information............................................................. 10 insulation and safety-related specifications.......................... 10 din en 60747-5-2 (vde 0884 part 2) insulation characteristics ............................................................................ 11 absolute maximum ratings ......................................................... 12 recommended operating conditions .................................... 12 esd caution................................................................................ 12 pin configurations and function descriptions ......................... 13 typical performance characteristics ........................................... 16 application information................................................................ 18 pc board layout ........................................................................ 18 propagation delay-related parameters................................... 18 dc correctness and magnetic field immunity........................... 18 power consumption .................................................................. 19 outline dimensions ....................................................................... 20 ordering guide .......................................................................... 20 revision history 10/06rev. d to rev. e added ADUM1411 and adum1412................................universal deleted adum1310 ...........................................................universal changes to features.......................................................................... 1 changes to specifications section.................................................. 3 updated outline dimensions ....................................................... 20 changes to ordering guide .......................................................... 20 3/06rev. c to rev. d added note 1 and changes to figure 2......................................... 1 changes to absolute maximum ratings ..................................... 11 11/05rev. spb to rev. c: initial version
adum1410/ADUM1411/adum1412 rev. e | page 3 of 20 specifications electrical characteristics5 v operation 4.5 v v dd1 5.5 v, 4.5 v v dd2 5.5 v; all min/max specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at t a = 25c, v dd1 = v dd2 = 5 v. 1 table 1. parameter symbol min typ max unit test conditions dc specifications input supply current per channel, quiescent i ddi (q) 0.50 0.73 ma output supply current per channel, quiescent i ddo (q) 0.38 0.53 ma adum1410, total supply current, four channels 2 dc to 2 mbps v dd1 supply current i dd1 (q) 2.4 3.2 ma dc to 1 mhz logic signal frequency v dd2 supply current i dd2 (q) 1.2 1.6 ma dc to 1 mhz logic signal frequency 10 mbps (brw grade only) v dd1 supply current i dd1 (10) 8.8 12 ma 5 mhz logic signal frequency v dd2 supply current i dd2 (10) 2.8 4.0 ma 5 mhz logic signal frequency ADUM1411, total supply current, four channels 2 dc to 2 mbps v dd1 supply current i dd1 (q) 2.2 2.8 ma dc to 1 mhz logic signal frequency v dd2 supply current i dd2 (q) 1.8 2.4 ma dc to 1 mhz logic signal frequency 10 mbps (brw grade only) v dd1 supply current i dd1 (10) 5.4 7.6 ma 5 mhz logic signal frequency v dd2 supply current i dd2 (10) 3.8 5.3 ma 5 mhz logic signal frequency adum1412, total supply current, four channels 2 dc to 2 mbps v dd1 or v dd2 supply current i dd1 (q) , i dd2 (q) 2.0 2.6 ma dc to 1 mhz logic signal frequency 10 mbps (brw grade only) v dd1 or v dd2 supply current i dd1 (10) , i dd2 (10) 4.6 6.5 ma 5 mhz logic signal frequency for all models input currents i ia , i ib , i ic , i id , i ctrl1 , i ctrl2 , i disable ?10 +0.01 +10 a 0 v ia ,v ib , v ic ,v id v dd1 or v dd2 , 0 v ctrl1 ,v ctrl2 v dd1 or v dd2 , v disable v dd1 logic high input threshold v ih 2.0 v logic low input threshold v il 0.8 v v dd1 , v dd2 ? 0.1 5.0 v i ox = ?20 a, v ix = v ixh logic high output voltages v oah , v obh , v och , v odh v dd1 , v dd2 ? 0.4 4.8 v i ox = ?4 ma, v ix = v ixh 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.04 0.1 v i ox = 400 a, v ix = v ixl logic low output voltages v oal , v obl , v ocl , v odl 0.2 0.4 v i ox = 4 ma, v ix = v ixl switching specifications ADUM1411arw and adum1412arw minimum pulse width 3 pw 1000 ns c l = 15 pf, cmos signal levels maximum data rate 4 1 mbps c l = 15 pf, cmos signal levels propagation delay 5 t phl , t plh 20 65 100 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh ? t phl | 5 pwd 40 ns c l = 15 pf, cmos signal levels propagation delay skew 6 t psk 50 ns c l = 15 pf, cmos signal levels channel-to-channel matching 7 t pskcd/od 50 ns c l = 15 pf, cmos signal levels
adum1410/ADUM1411/adum1412 rev. e | page 4 of 20 parameter symbol min typ max unit test conditions adum141xbrw minimum pulse width 3 pw 100 ns c l = 15 pf, cmos signal levels maximum data rate 4 10 mbps c l = 15 pf, cmos signal levels propagation delay 5 t phl , t plh 20 30 50 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh ? t phl | 5 pwd 5 ns c l = 15 pf, cmos signal levels change vs. temperature 5 ps/c c l = 15 pf, cmos signal levels propagation delay skew 6 t psk 30 ns c l = 15 pf, cmos signal levels channel-to-channel matching, codirectional channels 7 t pskcd 5 ns c l = 15 pf, cmos signal levels channel-to-channel matching, opposing-directional channels 7 t pskod 6 ns c l = 15 pf, cmos signal levels for all models output rise/fall time (10% to 90%) t r /t f 2.5 ns c l = 15 pf, cmos signal levels common-mode transient immunity at logic high output 8 |cm h | 25 35 kv/s v ix = v dd1 /v dd2 , v cm = 1000 v, transient magnitude = 800 v common-mode transient immunity at logic low output 8 |cm l | 25 35 kv/s v ix = 0 v, v cm = 1000 v, transient magnitude = 800 v refresh rate f r 1.2 mbps input enable time 9 t enable 2.0 s v ia , v ib , v ic , v id , = 0 or v dd1 input disable time 9 t disable 5.0 s v ia , v ib , v ic , v id , = 0 or v dd1 input dynamic supply current per channel 10 i ddi (d) 0.12 ma/mbps output dynamic supply current per channel 10 i ddo (d) 0.04 ma/mbps 1 all voltages are relative to their respective ground. 2 the supply current values for all four cha nnels are combined when running at identica l data rates. output supply current value s are specified with no output load present. the supply current associat ed with an individual channel op erating at a given data rate ca n be calculated as described in the power consumption section. see figure 8 through figure 10 for information on per-channel supply current as a functi on of data rate for unloaded and loaded conditions. see figure 11 through figure 15 for total v dd1 and v dd2 supply currents as a function of data rate for adum1410/adum1 411/adum1412 channel configurations. 3 the minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 4 the maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 5 t phl propagation delay is measured from the 50% level of the falling edge of the v ix signal to the 50% level of the falling edge of the v ox signal. t plh propagation delay is measured from the 50% level of the rising edge of the v ix signal to the 50% level of the rising edge of the v ox signal. 6 t psk is the magnitude of the worst-case difference in t phl or t plh that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 7 codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channe ls with inputs on the same side of the isolation barrier. opposi ng-directional channe l-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 8 cm h is the maximum common-mode voltage slew rate that can be sustained while maintaining v o > 0.8 v dd2 . cm l is the maximum common-mod e voltage slew rate that can be sustained while maintaining v o < 0.8 v. the common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. the transient magnitude is the range over which the common mode is slewed. 9 input enable time is the duration from when v disable is set low until the output states are guaranteed to match the input states in the absence of any input data logic transitions. if an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the much shorter duration as determined by the propagation delay specifications within this data sheet. input disable time is the d uration from when v disable is set high until the output states are guaranteed to reach their progr ammed output levels, as determined by the ctrl logic state (see tabl e 10). 10 dynamic supply current is the incremental amou nt of supply current required for a 1 mbps increase in signal data rate. see fig ure 8 through figure 10 for information on per-channel supply current for unloaded and loaded conditions. see the power consumption section for guidance on calculating the per-channel supply current for a given data rate.
adum1410/ADUM1411/adum1412 rev. e | page 5 of 20 electrical characteristics3 v operation 2.7 v v dd1 3.6 v, 2.7 v v dd2 3.6 v; all min/max specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at t a = 25c, v dd1 = v dd2 = 3.0 v. 1 table 2. parameter symbol min typ max unit test conditions dc specifications input supply current per channel, quiescent i ddi (q) 0.25 0.38 ma output supply current per channel, quiescent i ddo (q) 0.19 0.33 ma adum1410, total supply current, four channels 2 dc to 2 mbps v dd1 supply current i dd1 (q) 1.2 1.6 ma dc to 1 mhz logic signal frequency v dd2 supply current i dd2 (q) 0.8 1.0 ma dc to 1 mhz logic signal frequency 10 mbps (brw grade only) v dd1 supply current i dd1 (10) 4.5 6.5 ma 5 mhz logic signal frequency v dd2 supply current i dd2 (10) 1.4 1.8 ma 5 mhz logic signal frequency ADUM1411, total supply current, four channels 2 dc to 2 mbps v dd1 supply current i dd1 (q) 1.0 1.9 ma dc to 1 mhz logic signal frequency v dd2 supply current i dd2 (q) 0.9 1.7 ma dc to 1 mhz logic signal frequency 10 mbps (brw grade only) v dd1 supply current i dd1 (10) 3.1 4.5 ma 5 mhz logic signal frequency v dd2 supply current i dd2 (10) 2.1 3.0 ma 5 mhz logic signal frequency adum1412, total supply current, four channels 2 dc to 2 mbps v dd1 or v dd2 supply current i dd1 (q) , i dd2 (q) 1.0 1.8 ma dc to 1 mhz logic signal frequency 10 mbps (brw grade only) v dd1 or v dd2 supply current i dd1 (10) , i dd2 (10) 2.6 3.8 ma 5 mhz logic signal frequency for all models input currents i ia , i ib , i ic , i id , i ctrl1 , i ctrl2 , i disable ?10 +0.01 +10 a 0 v ia ,v ib , v ic ,v id v dd1 or v dd2 , 0 v ctrl1 ,v ctrl2 v dd1 or v dd2 , v disable v dd1 logic high input threshold v ih 1.6 v logic low input threshold v il 0.4 v v dd1 , v dd2 ? 0.1 3.0 v i ox = ?20 a, v ix = v ixh logic high output voltages v oah , v obh , v och , v odh v dd1 , v dd2 ? 0.4 2.8 v i ox = ?4 ma, v ix = v ixh 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.04 0.1 v i ox = 400 a, v ix = v ixl logic low output voltages v oal , v obl , v ocl , v odl 0.2 0.4 v i ox = 4 ma, v ix = v ixl switching specifications ADUM1411arw and adum1412arw minimum pulse width 3 pw 1000 ns c l = 15 pf, cmos signal levels maximum data rate 4 1 mbps c l = 15 pf, cmos signal levels propagation delay 5 t phl , t plh 20 75 100 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh ? t phl | 5 pwd 40 ns c l = 15 pf, cmos signal levels propagation delay skew 6 t psk 50 ns c l = 15 pf, cmos signal levels channel-to-channel matching 7 t pskcd/od 50 ns c l = 15 pf, cmos signal levels adum141xbrw minimum pulse width 3 pw 100 ns c l = 15 pf, cmos signal levels maximum data rate 4 10 mbps c l = 15 pf, cmos signal levels propagation delay 5 t phl , t plh 20 40 60 ns c l = 15 pf, cmos signal levels
adum1410/ADUM1411/adum1412 rev. e | page 6 of 20 parameter symbol min typ max unit test conditions pulse width distortion, |t plh ? t phl | 5 pwd 5 ns c l = 15 pf, cmos signal levels change vs. temperature 5 ps/c c l = 15 pf, cmos signal levels propagation delay skew 6 t psk 30 ns c l = 15 pf, cmos signal levels channel-to-channel matching, codirectional channels 7 t pskcd 5 ns c l = 15 pf, cmos signal levels channel-to-channel matching, opposing-directional channels 7 t pskod 6 ns c l = 15 pf, cmos signal levels for all models output rise/fall time (10% to 90%) t r /t f 2.5 ns c l = 15 pf, cmos signal levels common-mode transient immunity at logic high output 8 |cm h | 25 35 kv/s v ix = v dd1 /v dd2 , v cm = 1000 v, transient magnitude = 800 v common-mode transient immunity at logic low output 8 |cm l | 25 35 kv/s v ix = 0 v, v cm = 1000 v, transient magnitude = 800 v refresh rate 1.1 mbps input enable time 9 t enable 2.0 s v ia , v ib , v ic , v id = 0 or v dd1 input disable time 9 t disable 5.0 s v ia , v ib , v ic , v id = 0 or v dd1 input dynamic supply current per channel 10 i ddi (d) 0.07 ma/mbps output dynamic supply current per channel 10 i ddo (d) 0.02 ma/mbps 1 all voltages are relative to their respective ground. 2 the supply current values for all four cha nnels are combined when running at identica l data rates. output supply current value s are specified with no output load present. the supply current associat ed with an individual channel op erating at a given data rate ca n be calculated as described in the power consumption section. see figure 8 through figure 10 for information on per-channel supply current as a functi on of data rate for unloaded and loaded conditions. see figure 11 through figure 15 for total v dd1 and v dd2 supply currents as a function of data rate for adum1410/adum1 411/adum1412 channel configurations. 3 the minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 4 the maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 5 t phl propagation delay is measured from the 50% level of the falling edge of the v ix signal to the 50% level of the falling edge of the v ox signal. t plh propagation delay is measured from the 50% level of the rising edge of the v ix signal to the 50% level of the rising edge of the v ox signal. 6 t psk is the magnitude of the worst-case difference in t phl or t plh that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 7 codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channe ls with inputs on the same side of the isolation barrier. opposi ng-directional channe l-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 8 cm h is the maximum common-mode voltage slew rate that can be sustained while maintaining v o > 0.8 v dd2 . cm l is the maximum common-mod e voltage slew rate that can be sustained while maintaining v o < 0.8 v. the common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. the transient magnitude is the range over which the common mode is slewed. 9 input enable time is the duration from when v disable is set low until the output states are guaranteed to match the input states in the absence of any input data logic transitions. if an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the much shorter duration as determined by the propagation delay specifications within this data sheet. input disable time is the d uration from when v disable is set high until the output states are guaranteed to reach their progr ammed output levels, as determined by the ctrl logic state (see tabl e 10). 10 dynamic supply current is the incremental amou nt of supply current required for a 1 mbps increase in signal data rate. see fig ure 8 through figure 10 for information on per-channel supply current for unloaded and loaded conditions. see the power consumption section for guidance on calculating the per-channel supply current for a given data rate.
adum1410/ADUM1411/adum1412 rev. e | page 7 of 20 electrical characteristicsmixe d 5 v/3 v or 3 v/5 v operation 5 v/3 v operation 1 : 4.5 v v dd1 5.5 v, 2.7 v v dd2 3.6 v; 3 v/5 v operation: 2.7 v v dd1 3.6 v, 4.5 v v dd2 5.5 v; all min/max specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at t a = 25c; v dd1 = 3.0 v, v dd2 = 5 v or v dd1 = 5 v, v dd2 = 3.0 v. table 3. parameter symbol min typ max unit test conditions dc specifications input supply current per channel, quiescent i ddi (q) 5 v/3 v operation 0.50 0.73 ma 3 v/5 v operation 0.25 0.38 ma output supply current per channel, quiescent i ddo (q) 5 v/3 v operation 0.19 0.33 ma 3 v/5 v operation 0.38 0.53 ma adum1410, total supply current, four channels 2 dc to 2 mbps v dd1 supply current i dd1 (q) 5 v/3 v operation 2.4 3.2 ma dc to 1 mhz logic signal frequency 3 v/5 v operation 1.2 1.6 ma dc to 1 mhz logic signal frequency v dd2 supply current i dd2 (q) 5 v/3 v operation 0.8 1.0 ma dc to 1 mhz logic signal freq uency 3 v/5 v operation 1.2 1.6 ma dc to 1 mhz logic signal freq uency 10 mbps (brw grade only) v dd1 supply current i dd1 (10) 5 v/3 v operation 8.6 11 ma 5 mhz logic signal frequency 3 v/5 v operation 3.4 6.5 ma 5 mhz logic signal frequency v dd2 supply current i dd2 (10) 5 v/3 v operation 1.4 1.8 ma 5 mhz logic signal frequency 3 v/5 v operation 2.6 3.0 ma 5 mhz logic signal frequency ADUM1411, total supply current, four channels 2 dc to 2 mbps v dd1 supply current i dd1 (q) 5 v/3 v operation 2.2 2.8 ma dc to 1 mhz logic signal frequency 3 v/5 v operation 1.0 1.9 ma dc to 1 mhz logic signal frequency v dd2 supply current i dd2 (q) 5 v/3 v operation 0.9 1.7 ma dc to 1 mhz logic signal frequency 3 v/5 v operation 1.7 2.4 ma dc to 1 mhz logic signal frequency 10 mbps (brw grade only) v dd1 supply current i dd1 (10) 5 v/3 v operation 5.4 7.6 ma 5 mhz logic signal frequency 3 v/5 v operation 3.1 4.5 ma 5 mhz logic signal frequency v dd2 supply current i dd2 (10) 5 v/3 v operation 2.1 3.0 ma 5 mhz logic signal frequency 3 v/5 v operation 3.8 5.3 ma 5 mhz logic signal frequency adum1412, total supply current, four channels 2 dc to 2 mbps v dd1 supply current i dd1 (q) 5 v/3 v operation 2.0 2.6 ma dc to 1 mhz logic signal frequency 3 v/5 v operation 1.0 1.8 ma dc to 1 mhz logic signal frequency v dd2 supply current i dd2 (q) 5 v/3 v operation 1.0 1.8 ma dc to 1 mhz logic signal frequency 3 v/5 v operation 2.0 2.6 ma dc to 1 mhz logic signal frequency
adum1410/ADUM1411/adum1412 rev. e | page 8 of 20 parameter symbol min typ max unit test conditions 10 mbps (brw grade only) v dd1 supply current i dd1 (10) 5 v/3 v operation 4.6 6.5 ma 5 mhz logic signal frequency 3 v/5 v operation 2.6 3.8 ma 5 mhz logic signal frequency v dd2 supply current i dd2 (10) 5 v/3 v operation 2.6 3.8 ma 5 mhz logic signal frequency 3 v/5 v operation 4.6 6.5 ma 5 mhz logic signal frequency for all models input currents i ia , i ib , i ic , i id , i ctrl1 , i ctrl2 , i disable ?10 +0.01 +10 a 0 v ia ,v ib , v ic ,v id v dd1 or v dd2 , 0 v ctrl1 ,v ctrl2 v dd1 or v dd2 , v disable v dd1 logic high input threshold v ih 5 v/3 v operation 2.0 v 3 v/5 v operation 1.6 v logic low input threshold v il 5 v/3 v operation 0.8 v 3 v/5 v operation 0.4 v v dd1 , v dd2 ? 0.1 v dd1 , v dd2 v i ox = ?20 a, v ix = v ixh logic high output voltages v oah , v obh , v och , v odh v dd1 , v dd2 ? 0.4 v dd1 , v dd ? 0.2 v i ox = ?4 ma, v ix = v ixh 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.04 0.1 v i ox = 400 a, v ix = v ixl logic low output voltages v oal , v obl , v ocl , v odl 0.2 0.4 v i ox = 4 ma, v ix = v ixl switching specifications ADUM1411arw and adum1412arw minimum pulse width 3 pw 1000 ns c l = 15 pf, cmos signal levels maximum data rate 4 1 mbps c l = 15 pf, cmos signal levels propagation delay 5 t phl , t plh 25 70 100 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh ? t phl | 5 pwd 40 ns c l = 15 pf, cmos signal levels propagation delay skew 6 t psk 50 ns c l = 15 pf, cmos signal levels channel-to-channel matching 7 t pskcd/od 50 ns c l = 15 pf, cmos signal levels adum141xbrw minimum pulse width 3 pw 100 ns c l = 15 pf, cmos signal levels maximum data rate 4 10 mbps c l = 15 pf, cmos signal levels propagation delay 5 t phl , t plh 25 35 60 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh ? t phl | 5 pwd 5 ns c l = 15 pf, cmos signal levels change vs. temperature 5 ps/c c l = 15 pf, cmos signal levels propagation delay skew 6 t psk 30 ns c l = 15 pf, cmos signal levels channel-to-channel matching, codirectional channels 7 t pskcd 5 ns c l = 15 pf, cmos signal levels channel-to-channel matching, opposing-directional channels 7 t pskod 6 ns c l = 15 pf, cmos signal levels for all models output rise/fall time (10% to 90%) t r /t f c l = 15 pf, cmos signal levels 5 v/3 v operation 2.5 ns 3 v/5 v operation 2.5 ns common-mode transient immunity at logic high output 8 |cm h | 25 35 kv/s v ix = v dd1 /v dd2 , v cm = 1000 v, transient magnitude = 800 v common-mode transient immunity at logic low output 8 |cm l | 25 35 kv/s v ix = 0 v, v cm = 1000 v, transient magnitude = 800 v refresh rate f r 5 v/3 v operation 1.2 mbps 3 v/5 v operation 1.1 mbps input enable time 9 t enable 2.0 s v ia , v ib , v ic , v id = 0 or v dd1
adum1410/ADUM1411/adum1412 rev. e | page 9 of 20 parameter symbol min typ max unit test conditions input disable time 9 t disable 5.0 s v ia , v ib , v ic , v id = 0 or v dd1 input dynamic supply current per channel 10 i ddi (d) 5 v operation 0.12 ma/mbps 3 v operation 0.07 ma/mbps output dynamic supply current per channel 10 i ddi (d) 5 v operation 0.04 ma/mbps 3 v operation 0.02 ma/mbps 1 all voltages are relative to their respective ground. 2 the supply current values for all four cha nnels are combined when running at identica l data rates. output supply current value s are specified with no output load present. the supply current associat ed with an individual channel op erating at a given data rate ca n be calculated as described in the power consumption section. see figure 8 through figure 10 for information on per-channel supply current as a functi on of data rate for unloaded and loaded conditions. see figure 11 through figure 15 for total v dd1 and v dd2 supply currents as a function of data rate for adum1410/adum1 411/adum1412 channel configurations. 3 the minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 4 the maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 5 t phl propagation delay is measured from the 50% level of the falling edge of the v ix signal to the 50% level of the falling edge of the v ox signal. t plh propagation delay is measured from the 50% level of the rising edge of the v ix signal to the 50% level of the rising edge of the v ox signal. 6 t psk is the magnitude of the worst-case difference in t phl or t plh that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 7 codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channe ls with inputs on the same side of the isolation barrier. opposi ng-directional channe l-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 8 cm h is the maximum common-mode voltage slew rate that can be sustained while maintaining v o > 0.8 v dd2 . cm l is the maximum common-mod e voltage slew rate that can be sustained while maintaining v o < 0.8 v. the common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. the transient magnitude is the range over which the common mode is slewed. 9 input enable time is the duration from when v disable is set low until the output states are guaranteed to match the input states in the absence of any input data logic transitions. if an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the much shorter duration as determined by the propagation delay specifications within this data sheet. input disable time is the d uration from when v disable is set high until the output states are guaranteed to reach their progr ammed output levels, as determined by the ctrl logic state (see tabl e 10). 10 dynamic supply current is the incremental amou nt of supply current required for a 1 mbps increase in signal data rate. see fig ure 8 through figure 10 for information on per-channel supply current for unloaded and loaded conditions. see the power consumption section for guidance on calculating the per-channel supply current for a given data rate.
adum1410/ADUM1411/adum1412 rev. e | page 10 of 20 package characteristics table 4. parameter symbol min typ max unit test conditions resistance (input-to-output) 1 r i-o 10 12 capacitance (input-to-output) 1 c i-o 2.2 pf f = 1 mhz input capacitance 2 c i 4.0 pf ic junction-to-case thermal resistance, side 1 jci 33 c/w ic junction-to-case thermal resistance, side 2 jco 28 c/w thermocouple located at center of package underside 1 the adum141x device is considered a 2-te rminal device; pin 1 through pin 8 are sh orted together, and pin 9 through pin 16 are shorted together. 2 input capacitance is from any input data pin to ground. regulatory information the adum141x have been approved by the organizations listed in table 5 . table 5. ul 1 csa vde 2 (ADUM1411 and adum1412 pending) recognized under 1577 component recognition program 1 approved under csa component acceptance notice #5a certified according to din en 60747-5-2 (vde 0884 part 2): 2003-01 2 1 in accordance with ul1577, each adum141x is proof tested by a pplying an insulation test voltage 3000 v rms for 1 second (curr ent leakage detectio n limit = 5 a). 2 in accordance with din en 60747-5- 2, each adum141x is proof tested by applying an insulation te st voltage 1050 v peak for 1 s econd (partial discharge detection limit = 5 pc). the * marking branded on the co mponent designates din en 60747-5-2 approval. insulation and safety-related specifications table 6. parameter symbol value unit conditions rated dielectric insulation voltage 2500 v rms 1 minute duration minimum external air gap (clearance) l(i01) 7.7 min mm measured from input termin als to output terminals, shortest distance through air minimum external tracking (creepage) l(i02) 8.1 min mm measured from input termin als to output terminals, shortest distance path along body minimum internal gap (internal clearance) 0.017 min mm insulation distance through insulation tracking resistance (comparative tracking index) cti >175 v din iec 112/vde 0303 part 1 isolation group iiia material group (din vde 0110, 1/89, table 1)
adum1410/ADUM1411/adum1412 rev. e | page 11 of 20 din en 60747-5-2 (vde 0884 part 2) insulation characteristics these isolators are suitable for basic electrical isolation only within the safety limit data. maintenance of the safety data i s ensured by protective circuits. the * marking on packages denotes din en 60747-5-2 approval. table 7. description conditions symbol characteristic unit installation classification per din vde 0110 for rated mains voltage 150 v rms i to iv 1 for rated mains voltage 300 v rms i to iii for rated mains voltage 400 v rms i to ii climatic classification 40/105/21 pollution degree (din vde 0110, table 1) 2 maximum working insulation voltage v iorm 560 v peak input-to-output test voltage, method b1 v iorm 1.875 = v pr , 100% production test, t m = 1 sec, partial discharge < 5 pc v pr 1050 v peak input-to-output test voltage, method a v iorm 1.6 = v pr , t m = 60 sec, partial discharge < 5 pc v pr after environmental tests subgroup 1 896 v peak after input and/or safety test subgroup 2 and subgroup 3 v iorm 1.2 = v pr , t m = 60 sec, partial discharge < 5 pc 672 v peak highest allowable overvoltage transient overvoltage, t tr = 10 seconds v tr 4000 v peak safety-limiting values maximum value allowed in the event of a failure; see figure 7 case temperature t s 150 c side 1 current i s1 265 ma side 2 current i s2 335 ma insulation resistance at t s v io = 500 v r s >10 9 1 see din vde 0110 for definition of classification 1 thr ough classification iv listed in the ch aracteristic column.
adum1410/ADUM1411/adum1412 rev. e | page 12 of 20 absolute maximum ratings ambient temperature (t a ) = 25c, unless otherwise noted. table 8. parameter rating storage temperature (t st ) ?65c to +150c ambient operating temperature (t a ) ?40c to +105c supply voltages 1 (v dd1 , v dd2 ) ?0.5 v to +7.0 v input voltages 1, 2 (v ia , v ib , v ic , v id , v e1 , v e2 ) ?0.5 v to v ddi + 0.5 v output voltages 1, 2 (v oa , v ob , v oc , v od ) ?0.5 v to v ddo + 0.5 v average output current per pin 3 side 1 (i o1 ) ?18 ma to +18 ma side 2 (i o2 ) ?22 ma to +22 ma common-mode transients 4 ?100 kv/s to +100 kv/s 1 all voltages are relative to their respective ground. 2 v ddi and v ddo refer to the supply voltages on the input and output sides of a given channel, respectively. see the pc board layout section. 3 see figure 7 for maximum rated current values for various temperatures. 4 refers to common-mode transients across the insulation barrier. common- mode transients exceeding the abso lute maximum ratings may cause latch- up or permanent damage. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operat ing conditions all voltages are relative to their respective ground. see the dc correctness and magnetic field immunity section for information on immunity to external magnetic fields. table 9. parameter symbol min max unit operating temperature t a ?40 +105 c supply voltages v dd1 , v dd2 2.7 5.5 v input signal rise and fall times 1.0 ms esd caution table 10. truth table (positive logic) v ix input 1 ctrl input 2 v disable state 3 v ddi state 4 v ddo state 5 v ox output 1 notes h x l or nc powered powered h no rmal operation, data is high. l x l or nc powered powered l no rmal operation, data is low. x h or nc h x powered h inputs disabled. outputs are in the default state as determined by ctrl. x l h x powered l inputs disabled. outputs are in the default state as determined by ctrl. x h or nc x unpowered powered h input unpowered. outputs are in the de fault state as determined by ctrl. outputs return to input state within 1 s of v ddi power restoration. see the pin configurations and function descriptions section for more details. x l x unpowered powered l input unpowered. outputs are in the de fault state as determined by ctrl. outputs return to input state within 1 s of v ddi power restoration. see the pin configurations and function descriptions section for more details. x x x powered unpowered z output unpowered. output pins are in high impedance state. outputs return to input state within 1 s of v ddo power restoration. see the pin configurations and function descriptions section for more details. 1 v ix and v ox refer to the input and output signals of a given channel (a, b, c, or d). 2 ctrl refers to the ctrl signal on the input side of a given channel (a, b, c, or d). 3 available only on adum1410. 4 v ddi refers to the power supply on the input side of a given channel (a, b, c, or d). 5 v ddo refers to the power supply on the output side of a given channel (a, b, c, or d).
adum1410/ADUM1411/adum1412 rev. e | page 13 of 20 pin configurations and function descriptions v dd1 1 gnd 1 * 2 v ia 3 v ib 4 v dd2 16 gnd 2 * 15 v oa 14 v ob 13 v ic 5 v oc 12 v id 6 v od 11 disable 7 ctrl 10 gnd 1 * 8 gnd 2 * 9 adum1410 top view (not to scale) * pin 2 and pin 8 are internally connected. connecting both to gnd 1 is recommended. pin 9 and pin 15 are internally connected. connecting both to gnd 2 is recommended. 0 6502-005 figure 4. adum1410 pin configuration table 11. adum1410 pin function descriptions pin no. mnemonic description 1 v dd1 supply voltage for isolator side 1, 2.7 v to 5.5 v. 2 gnd 1 ground 1. ground reference for isolator side 1. pin 2 and pin 8 are internally connected, and connecting both to gnd 1 is recommended. 3 v ia logic input a. 4 v ib logic input b. 5 v ic logic input c. 6 v id logic input d. 7 disable input disable. disables the isolator inp uts and halts the dc refresh circuits. outp uts take on the logic state determined by ctrl. 8 gnd 1 ground 1. ground reference for isolator side 1. pin 2 and pin 8 are internally connected, and connecting both to gnd 1 is recommended. 9 gnd 2 ground 2. ground reference for isolator side 2. pin 9 and pin 15 are internally connected, and connecting both to gnd 2 is recommended. 10 ctrl default output control. controls the logic state th e outputs assume when the input power is off. v oa , v ob , v oc , and v od outputs are high when ctrl is high or disconnected and v dd1 is off. v oa , v ob , v oc , and v od outputs are low when ctrl is low and v dd1 is off. when v dd1 power is on, this pin has no effect. 11 v od logic output d. 12 v oc logic output c. 13 v ob logic output b. 14 v oa logic output a. 15 gnd 2 ground 2. ground reference for isolator side 2. pin 9 and pin 15 are internally connected, and connecting both to gnd 2 is recommended. 16 v dd2 supply voltage for isolator side 2, 2.7 v to 5.5 v.
adum1410/ADUM1411/adum1412 rev. e | page 14 of 20 v dd1 1 gnd 1 * 2 v ia 3 v ib 4 v dd2 16 gnd 2 * 15 v oa 14 v ob 13 v ic 5 v oc 12 v od 6 v id 11 ctrl 1 7 ctrl 2 10 gnd 1 * 8 gnd 2 * 9 ADUM1411 top view (not to scale) * pin 2 and pin 8 are internally connected. connecting both to gnd 1 is recommended. pin 9 and pin 15 are internally connected. connecting both to gnd 2 is recommended. 06502-006 figure 5. ADUM1411 pin configuration table 12. ADUM1411 pin function descriptions pin no. mnemonic description 1 v dd1 supply voltage for isolator side 1, 2.7 v to 5.5 v. 2 gnd 1 ground 1. ground reference for isolator side 1. pin 2 and pin 8 are internally connected, and connecting both to gnd 1 is recommended. 3 v ia logic input a. 4 v ib logic input b. 5 v ic logic input c. 6 v od logic output d. 7 ctrl 1 default output control. controls the logic state th e outputs assume when the input power is off. v od output is high when ctrl 1 is high or disconnected and v dd2 is off. v od output is low when ctrl 1 is low and v dd2 is off. when v dd2 power is on, this pin has no effect. 8 gnd 1 ground 1. ground reference for isolator side 1. pin 2 and pin 8 are internally connected, and connecting both to gnd 1 is recommended. 9 gnd 2 ground 2. ground reference for isolator side 2. pin 9 and pin 15 are internally connected, and connecting both to gnd 2 is recommended. 10 ctrl 2 default output control. controls the logic state th e outputs assume when the input power is off. v oa , v ob , and v oc outputs are high when ctrl 2 is high or disconnected and v dd1 is off. v oa , v ob , and v oc outputs are low when ctrl 2 is low and v dd1 is off. when v dd1 power is on, this pin has no effect. 11 v id logic input d. 12 v oc logic output c. 13 v ob logic output b. 14 v oa logic output a. 15 gnd 2 ground 2. ground reference for isolator side 2. pin 9 and pin 15 are internally connected, and connecting both to gnd 2 is recommended. 16 v dd2 supply voltage for isolator side 2, 2.7 v to 5.5 v.
adum1410/ADUM1411/adum1412 rev. e | page 15 of 20 v dd1 1 gnd 1 * 2 v ia 3 v ib 4 v dd2 16 gnd 2 * 15 v oa 14 v ob 13 v oc 5 v ic 12 v od 6 v id 11 ctrl 1 7 ctrl 2 10 gnd 1 * 8 gnd 2 * 9 adum1412 top view (not to scale) * pin 2 and pin 8 are internally connected. connecting both to gnd 1 is recommended. pin 9 and pin 15 are internally connected. connecting both to gnd 2 is recommended. 0 6502-007 figure 6. adum1412 pin configuration table 13. adum1412 pin function descriptions pin no. mnemonic description 1 v dd1 supply voltage for isolator side 1, 2.7 v to 5.5 v. 2 gnd 1 ground 1. ground reference for isolator side 1. pin 2 and pin 8 are internally connected, and connecting both to gnd 1 is recommended. 3 v ia logic input a. 4 v ib logic input b. 5 v oc logic output c. 6 v od logic output d. 7 ctrl 1 default output control. controls the logic state th e outputs assume when the input power is off. v oc and v od outputs are high when ctrl 1 is high or disconnected and v dd2 is off. v oc and v od outputs are low when ctrl 1 is low and v dd2 is off. when v dd2 power is on, this pin has no effect. 8 gnd 1 ground 1. ground reference for isolator side 1. pin 2 and pin 8 are internally connected, and connecting both to gnd 1 is recommended. 9 gnd 2 ground 2. ground reference for isolator side 2. pin 9 and pin 15 are internally connected, and connecting both to gnd 2 is recommended. 10 ctrl 2 default output control. controls the logic state th e outputs assume when the input power is off. v oa and v ob outputs are high when ctrl 2 is high or disconnected and v dd1 is off. v oa and v ob outputs are low when ctrl 2 is low and v dd1 is off. when v dd1 power is on, this pin has no effect. 11 v id logic input d. 12 v ic logic input c. 13 v ob logic output b. 14 v oa logic output a. 15 gnd 2 ground 2. ground reference for isolator side 2. pin 9 and pin 15 are internally connected, and connecting both to gnd 2 is recommended. 16 v dd2 supply voltage for isolator side 2, 2.7 v to 5.5 v.
adum1410/ADUM1411/adum1412 rev. e | page 16 of 20 typical performance characteristics case temperature (c) safety-limiting current (ma) 0 0 350 300 250 200 150 100 50 50 100 150 200 side #1 side #2 06502-004 figure 7. thermal derating curve, dependence of safety-limiting values with case temperature per din en 60747-5-2 data rate (mbps) current/channel (ma) 0 0 1.0 0.5 1.5 2.0 26 8 41 0 5v 3v 06502-008 figure 8. typical supply current per input channel vs. data rate for 5 v and 3 v operation data rate (mbps) current/channel (ma) 0 0 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 26 8 41 5v 3v 0 06502-009 figure 9. typical supply current pe r output channel vs. data rate for 5 v and 3 v operation (no output load) data rate (mbps) current/channel (ma) 0 0 1.4 1.2 1.0 0.8 0.6 0.4 0.2 26 8 41 5v 3v 0 06502-010 figure 10. typical supply current pe r output channel vs. data rate for 5 v and 3 v operation (15 pf output load) data rate (mbps) current (ma) 0 0 10 8 6 4 2 26 8 41 5v 3v 0 06502-011 figure 11. typical adum1410 v dd1 supply current vs. data rate for 5 v and 3 v operation data rate (mbps) current (ma) 0 0 10 8 6 4 2 26 8 41 5v 3v 0 06502-012 figure 12. typical adum1410 v dd2 supply current vs. data rate for 5 v and 3 v operation
adum1410/ADUM1411/adum1412 rev. e | page 17 of 20 0 data rate (mbps) current (ma) 0 0 10 8 6 4 2 26 8 41 5v 3v 06502-013 figure 13. typical ADUM1411 v dd1 supply current vs. data rate for 5 v and 3 v operation data rate (mbps) current (ma) 0 0 10 8 6 4 2 26 8 41 5v 3v 0 06502-014 figure 14. typical ADUM1411 v dd2 supply current vs. data rate for 5 v and 3 v operation data rate (mbps) current (ma) 0 0 10 8 6 4 2 26 8 41 5v 3v 0 06502-015 figure 15. typical adum1412 v dd1 or v dd2 supply current vs. data rate for 5 v and 3 v operation
adum1410/ADUM1411/adum1412 rev. e | page 18 of 20 application information pc board layout the adum141x digital isolator requires no external interface circuitry for the logic interfaces. power supply bypassing is strongly recommended at the input and output supply pins (see figure 16 ). bypass capacitors are most conveniently con- nected between pin 1 and pin 2 for v dd1 , and between pin 15 and pin 16 for v dd2 . the capacitor value should be between 0.01 f and 0.1 f. the total lead length between both ends of the capacitor and the input power supply pin should not exceed 20 mm. bypassing between pin 1 and pin 8 and between pin 9 and pin 16 should also be considered unless the ground pair on each package side is connected close to the package. v dd1 gnd 1 v ia v ib v ic v id disable gnd 1 v dd2 gnd 2 v oa v ob v oc v od ctrl gnd 2 0 6502-017 figure 16. recommended printed circuit board layout in applications involving high common-mode transients, it is important to minimize board coupling across the isolation barrier. furthermore, design the board layout such that any coupling that does occur equally affects all pins on a given component side. failure to ensure this can cause voltage differentials between pins exceeding the absolute maximum ratings of the device, thereby leading to latch-up or permanent damage. propagation delay-related parameters propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. the input to output propagation delay time for a high to low transition may differ from the propagation delay time of a low to high transition. input ( v ix ) output (v ox ) t plh t phl 50% 50% 06502-018 figure 17. propagation delay parameters pulse width distortion is the maximum difference between these two propagation delay values, and it is an indication of how accurately the timing of the input signal is preserved. channel-to-channel matching refers to the maximum amount the propagation delay differs between channels within a single adum141x component. propagation delay skew refers to the maximum amount the propagation delay differs between multiple adum141x components operating under the same conditions. dc correctness and magnetic field immunity positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder using the transformer. the decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. in the absence of logic transitions at the input for more than 2 s, a periodic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. if the decoder receives no internal pulses of more than approximately 5 s, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see table 10 ) by the watchdog timer circuit. the magnetic field immunity of the adum141x is determined by the changing magnetic field which induces a voltage in the transformers receiving coil large enough to either falsely set or reset the decoder. the following analysis defines the conditions under which this can occur. the 3 v operating condition of the adum141x is examined because it represents the most suscep- tible mode of operation. the pulses at the transformer output have an amplitude greater than 1.0 v. the decoder has a sensing threshold at about 0.5 v, thus establishing a 0.5 v margin in which induced voltages can be tolerated. the voltage induced across the receiving coil is given by v = ( ?d/dt ) r n 2 ; n = 1, 2, , n where: is magnetic flux density (gauss). n is the number of turns in the receiving coil. r n is the radius of the n th turn in the receiving coil (cm). given the geometry of the receiving coil in the adum141x and an imposed requirement that the induced voltage be, at most, 50% of the 0.5 v margin at the decoder, a maximum allowable magnetic field at a given frequency can be calculated. the result is shown in figure 18 . magnetic field frequency (hz) 100 maximum allowable magnetic flux density (kgauss) 0.001 1m 10 0.01 1k 10k 10m 0.1 1 100m 100k 06502-019 figure 18. maximum allowable external magnetic flux density
adum1410/ADUM1411/adum1412 rev. e | page 19 of 20 for example, at a magnetic field frequency of 1 mhz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 v at the receiving coil. this is about 50% of the sensing threshold and does not cause a faulty output transition. similarly, if such an event occurs during a transmitted pulse (and was of the worst-case polarity), it reduces the received pulse from >1.0 v to 0.75 vstill well above the 0.5 v sensing threshold of the decoder. the preceding magnetic flux density values correspond to specific current magnitudes at given distances from the adum141x transformers. figure 19 expresses these allowable current magnitudes as a function of frequency for selected distances. as shown, the adum141x is extremely immune and can be affected only by extremely large currents operated at high frequency very close to the component. for the 1 mhz example noted, a 0.5 ka current needed to be placed 5 mm away from the adum141x to affect the operation of the component. magnetic field frequency (hz) maximum allowable current (ka) 1000 100 10 1 0.1 0.01 1k 10k 100m 100k 1m 10m distance = 5mm distance = 1m distance = 100mm 06502-020 figure 19. maximum allowable current for various current-to-adum141x spacings note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce error voltages sufficiently large enough to trigger the thresholds of succeeding circuitry. care should be taken in the layout of such traces to avoid this possibility. power consumption the supply current at a given channel of the adum141x isolator is a function of the supply voltage, the data rate of the channel, and the output load of the channel. for each input channel, the supply current is given by i ddi = i ddi ( q ) f 0.5 f r i ddi = i ddi (d) (2 f ? f r ) + i ddi ( q ) f > 0.5 f r for each output channel, the supply current is given by i ddo = i ddo ( q ) f 0.5 f r i ddo = ( i ddo ( d ) + (0.5 10 ?3 ) c l v ddo ) (2 f ? f r ) + i ddo ( q ) f > 0.5 f r where: i ddi (d) , i ddo (d) are the input and output dynamic supply currents per channel (ma/mbps). c l is the output load capacitance (pf). v ddo is the output supply voltage (v). f is the input logic signal frequency (mhz); it is half of the input data rate expressed in units of mbps. f r is the input stage refresh rate (mbps). i ddi (q) , i ddo (q) are the specified input and output quiescent supply currents (ma). to calculate the total v dd1 and v dd2 supply current, the supply currents for each input and output channel corresponding to v dd1 and v dd2 are calculated and totaled. figure 8 and figure 9 provide per-channel supply currents as a function of data rate for an unloaded output condition. figure 10 provides per- channel supply current as a function of data rate for a 15 pf output condition. figure 11 through figure 15 provide total v dd1 and v dd2 supply current as a function of data rate for adum1410/ADUM1411/adum1412 channel configurations.
adum1410/ADUM1411/adum1412 rev. e | page 20 of 20 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-013- aa 060606-a 10.50 (0.4134) 10.10 (0.3976) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0 . 5 0 ( 0 . 0 1 9 7 ) 0 . 2 5 ( 0 . 0 0 9 8 ) 1.27 (0.0500) 0.40 (0.0157) c oplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) seating plane 8 0 16 9 8 1 1.27 (0.0500) bsc 45 figure 20. 16-lead standard small outline package [soic_w] wide body (rw-16) dimensions shown in millimeters and (inches) ordering guide model number of inputs, v dd1 side number of inputs, v dd2 side maximum data rate maximum propagation delay, 5 v maximum pulse width distortion temperature range package description package option adum1410brwz 1 4 0 10 mbps 50 ns 5 ns ?40 c to +105 c 16-lead soic_w, wide body rw-16 adum1410brwz-rl 1 4 0 10 mbps 50 ns 5 ns ?40 c to +105 c 16-lead soic_w, wide body, 13 reel rw-16 ADUM1411arwz 1 3 1 1 mbps 100 ns 40 ns ?40 c to +105 c 16-lead soic_w, wide body rw-16 ADUM1411arwz-rl 1 3 1 1 mbps 100 ns 40 ns ?40 c to +105 c 16-lead soic_w, wide body, 13 reel rw-16 ADUM1411brwz 1 3 1 10 mbps 50 ns 5 ns ?40 c to +105 c 16-lead soic_w, wide body rw-16 ADUM1411brwz-rl 1 3 1 10 mbps 50 ns 5 ns ?40 c to +105 c 16-lead soic_w, wide body, 13 reel rw-16 adum1412arwz 1 2 2 1 mbps 100 ns 40 ns ?40 c to +105 c 16-lead soic_w, wide body rw-16 adum1412arwz-rl 1 2 2 1 mbps 100 ns 40 ns ?40 c to +105 c 16-lead soic_w, wide body, 13 reel rw-16 adum1412brwz 1 2 2 10 mbps 50 ns 5 ns ?40 c to +105 c 16-lead soic_w, wide body rw-16 adum1412brwz-rl 1 2 2 10 mbps 50 ns 5 ns ?40 c to +105 c 16-lead soic_w, wide body, 13 reel rw-16 1 z = pb-free part. ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d06502-0-10/06(e)

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